The present invention relates to a switching circuit for analog signals composed of field effect transistors. More precisely, it involves a gate circuit to switch analog signals ON and OFF by field effect transistors. The distortion of signals passing through the circuit is reduced by avoiding the unsymmetrical characteristics of the internal resistance when the circuit is in the ON state.
Switching of analog signals is performed generally by relays, but recently it has become important to handle analog signals by semiconductor devices. In this case, distortion of the signal becomes an important factor. Namely, the signal passing through the relay did not suffer from distortion, but when the signal passed through semiconductor devices, it suffered from distortion.
One approach to overcome this difficulty is to employ only a small signal. This is because, even if the transfer characteristic is not linear, a small signal amplitude is not distorted so much. But the need for a solid state switching device is increasing, because of its small size, quick response, small operating power, high reliability, economy and so on. Accordingly, it is required to provide for larger amplitude signals.
For switching signals, field effect transistors (FET) are widely used. But in a circuit which switches analog signals according to the ON and OFF states of a FET, the internal resistance of the FET when it is in the ON state (on-resistance) varies according to the voltage between source and drain (source-drain voltage) and the polarity of the signals, which cause distortion of the signals passing through the FET.
FIG. 1 shows an example of a prior art switching circuit for analog signals. In the figure, J.sub.0 designates a p-channel type FET for switching signals, I.sub.D is a constant current source for supplying current to the gate G of the FET J.sub.0 and so on. E.sub.K is a control voltage source for varying the conductivity of the FET J.sub.0 and for shifting the state of J.sub.0 ON and OFF.
The fundamental switching process is performed by switching the FET J.sub.0 to the ON and OFF states. Namely, when the control voltage E.sub.K is high, the channel between the source S and the drain D of the FET J.sub.0 is pinched off by an extended depletion layer formed by a high gate voltage, and the switch is OFF (namely, the gate is closed). On the contrary, when the control voltage E.sub.K is low, the depletion layer is narrowed, and the switch is ON (the gate is opened). Accordingly, the switching of the gate ON and OFF is determined by the low or high state of the control voltage.
A FET J.sub.1 in FIG. 1 detects the source voltage of the FET J.sub.0 and feeds it back to the gate G of the FET J.sub.0 in order to keep the voltage between the gate and source of J.sub.0 (V.sub.GS0) constant independent of the source voltage.
The drain current of each FET has saturation characteristics as shown in FIG. 2. This shows the drain current I.sub.D against the source-drain voltage V.sub.DS, for various values of the voltage between the gate and source (gate-source voltage), V.sub.GS. As can be seen in the figure, the drain current has a saturation region and an unsaturation region. In the saturation region, the drain current I.sub.D can be expressed as ##EQU1## wherein V.sub.GS is the gate-source voltage, I.sub.DSS is the saturation current of the drain when V.sub.GS =0 and V.sub.P is the pinch-off voltage.
In the unsaturation region, the drain current I.sub.D is given as ##EQU2## wherein V.sub.DS is the source-drain voltage, and R.sub.min is the resistance between the source and drain when V.sub.DS =0 and V.sub.GS =0. These equations are well known in the prior art. A more detailed description is provided, for example, in Physics of Semiconductor Devices, published by John Wiley & Sons, Inc., N.Y., 1969.
In the circuit shown in FIG. 1, if the FET J.sub.1 is operated in a saturation region in accordance with equation (1) and if its drain current is fixed by the constant current source I.sub.D, then the gate-source voltage V.sub.GS1 of the FET J.sub.1 is also fixed. Thus, in the circuit of FIG. 1, when the voltage of the gate of the FET J.sub.1 follows changes in the source voltage of transistor J.sub.0, the bottom terminal (the negative terminal) of the control voltage source E.sub.K also follows those changes. Consequently, the top terminal of the control voltage source E.sub.K follows the changes in the source voltage of the transistor J.sub.0, which means that the gate voltage of the FET J.sub.0 follows those changes, thereby to maintain V.sub.GS0 constant.
The inner resistance R.sub.ON between the source and drain of the transistor J.sub.0 when it is in the ON (conductive) state is given by ##EQU3## It should be noted that equation (2) is expressed in terms of absolute value, while on the other hand, for a general p-channel FET, the gate electrode G is positively biased with respect to the source electrode S, and the drain electrode D is negatively biased (V.sub.DS) with respect to the source electrode. Therefore, V.sub.DS0 should be replaced in the above equation by -V.sub.DS0. Therefore ##EQU4## in which V.sub.DS0 &lt;0.
In the case of V.sub.DS0 &gt;0, that is, wherein the drain voltage is higher than the source voltage, the drain current I.sub.D of the p-channel FET is controlled by the gate-drain voltage V.sub.GD. The direction of I.sub.D0 is reversed. Therefore in this case V.sub.GS0, V.sub.DS0 and I.sub.D0 of the foregoing equations should be replaced by V.sub.GD0, -V.sub.DS0 and I.sub.D0 respectively. So, from the equation above equation (3) ##EQU5##
With the same reasoning as for equation (3), in order to express the equation using a positive value of V.sub.DS0, it is necessary to replace -V.sub.DS0 by V.sub.DS0. So the equation above becomes ##EQU6## As has been noted above, V.sub.GS0 is a constant, EQU V.sub.GD0 =V.sub.GS0 -V.sub.DS0
Introducing this relation into equation (4), R.sub.ON is given as ##EQU7##
This is the same equation as equation (3). So, the equation (3) can be applied not only for the negative value of V.sub.DS0, but also for all values of V.sub.DS0 regardless of whether its sign is + or -. In FIG. 3, the curve A shows the above relation of equation (5), under a condition of .vertline.V.sub.p .vertline.&gt;.vertline.V.sub.GS .vertline., and .vertline.V.sub.p .vertline.&gt;.vertline.V.sub.GD .vertline.. As can be seen in the figure, in the region of V.sub.DS &lt;0, R.sub.ON increases. In the region of V.sub.DS &gt;0, R.sub.ON decreases compared to the value at V.sub.DS =0, showing asymmetric characteristics. For the curve A of FIG. 3, equation (5) was calculated in a condition of V.sub.p =1.5 volt, V.sub.GS0 =0.8 volt. The asymmetric characteristics of R.sub.ON causes the asymmetric characteristics of current and voltage of signals passing through the FET, and that causes the distortion.